This application is based upon and claims priority of Japanese Patent Application No. 2000-141072, filed, the contents being incorporated herein by reference.
1. Field of the Invention
The present invention relates to a technique for improving data holding of a non-volatile memory such as EEPROM (Electrical Erasable and Programmable Read Only Memory) and flash memory (an EEPROM capable of simultaneously erasing plural memory data in a memory cell block by one action). In more detail, the present invention relates to improvement of technique for making data reading characteristic more reliable by prohibiting memory data from easily deteriorating once after the data is stored into EEPROM memory cell, e.g., flash memory cell.
2. Discussion of the Related Art
A memory cell used in the non-volatile memory such as EEPROM and flash memory has generally been formed, according to the related art, with a double-gate structure including a floating gate electrode and a control gate electrode, provided in the laminating method holding a thin insulation film between these gate electrodes. However, recently the complicated manufacturing process of such double-gate structure distinctively impedes ultra-micro-miniaturization and attention is now paid to the new technique for realizing single gate structure as the gate structure.
In the case of such single gate type non-volatile memory, a material that can store charges, for example, a material of nitride film group is employed as a gate insulation film covered between a silicon substrate and a gate electrode and thereby charges may be stored by seizing the charges with the gate insulation film that can store charges in place of using a floating gate. As an example of a single gate type non-volatile semiconductor memory, a SONOS type memory has been proposed. This SONOS type memory has the laminated structure of silicon oxide film (SiO), silicon nitride film (SiN) and silicon oxide film (SiO) as a structure of gate insulation film and data recording can be realized by inputting or outputting the charges to or from the silicon nitride film (SiN). (The silicon oxide film (SiO) nearer to the silicon substrate is called the first gate oxide film and that nearer to the gate electrode is called the second gate oxide film.)
For such SONOS type memory cell, a cell layout in which the source and drain are connected in parallel is generally employed. In this layout, the sources and drains of a plurality of adjacent memory cells are connected in parallel to form the columns and a column is defined as a bit line. The bit line is connected to a sense amplifier via the selection gate. The gates of the adjacent memory cells in the column direction are coupled with a single wire as the word line.
Operations of the non-volatile semiconductor memory of such SONOS type memory cell are as follows.
[Data Write Operation]
Data write operation is performed by applying the write potential Vdp (about 5V) to the bit line connected to the drain of the selected cell, giving 0V to the bit line connected to the source and applying a word line Vwp (about 10V) to the word line. In this case, the bit line and word line of non-selected cell are floated to avoid the data writing. When the data write operation is performed as explained above, hot electrons are generated at the area near the drain in the selected cell. The hot electrons are trapped into the nitride film near to the drain, exceeding the barrier of the first gate oxide film. Thereby, a threshold voltage of the selected cell shifts in the positive direction. This condition is defined as xe2x80x9c0xe2x80x9d.
[Data Erase Operation]
The data erase operation is performed for all memory cells of the selected block by applying Vwe (about xe2x88x923V) to all word lines of the selected block and setting all bit lines to Vbe (about 7V). Thereby, electrons trapped in the nitride film are removed and the threshold voltage is shifted in the negative direction. This condition is defined as xe2x80x9c1xe2x80x9d.
[Data Read Operation]
The data read operation is performed by applying Vwr (about 4V) to the word line connected to the selected memory cell, applying a read potential Vbr (about 1V) to the bit line connected to the drain and giving 0V to the bit line connected to the source. However, the relationship between the drain and source during the read operation is inverted from the relationship in the data write operation, because electrons are trapped at the area near the diffused layer defined as the drain at the time of data write operation. Namely, a larger shift of threshold value can be obtained when the drain and source are inverted. Data read is determined with the absolute value of a current flowing into the selected memory cell.
[Data Verifying Operation]
In the case of data verifying operation, after completion of the write operation explained above, the verifying operation is performed to confirm whether write operation is sufficient or not. If write operation is insufficient, re-writing is performed to such cell. The verifying operation and write operation are repeated until all data are written. In the case of erasing the verifying operation, the verifying operation is performed after the erase operation explained above. If erase is insufficient, the erase operation is executed again. These operations are performed until the erase operation is conducted sufficiently.
The SONOS type memory cell has a characteristic, unlike the floating gate type memory cell, to trap the electrons to the insulation film. Density of trapped charges is approximated as about 2.0xc3x971012cmxe2x88x922 to 1.0xc3x971013cmxe2x88x922. This density is near to the interface level density at the interface of the substrate and first oxide film when the memory cell is deteriorated. Therefore, density of trap site in the SONOS type memory cell or at the interface with the substrate can be compared with the trap site in the nitride film and therefore gives a large influence on the transistor characteristic. When the write/erase characteristic explained above is repeated, the first gate oxide film and interface are deteriorated and an extra trap site is increased. Namely, here rises a problem that while operation is continued, the memory cell characteristic, particularly the read characteristic is deviated from the initial characteristic.
This problem is not limited to the SONOS type memory cell but is true to all memory cells in which an insulation film that can easily capture the electrons more than the silicon oxide film is formed on a gate oxide film and this insulation film is used as the electron trap.
As explained above, in the SONOS type non-volatile memory cell of the related art and also in the memory cell of the type to trap charges with a gate insulation film, extra trap site increases at the first gate oxide film and the interface thereof, and the memory cell read characteristic is thereby extremely deteriorated. Such problems have been appeared.
Referring to FIG. 1
FIG. 1 is a graph (No. 1) showing the read characteristic of the SONOS type non-volatile memory of the related art, indicating, on the same graph for the purpose of comparison, the characteristic (white square points) in the condition to start the application (initial condition) and the operation (xe2x80x9ccyclingxe2x80x9d operation) to repeat the data write and erase operations for 10,000 times (black circular points) wherein the gate voltage (vg) is plotted on the horizontal axis and the drain current (Id) on the vertical axis. As will be apparent from FIG. 1, in the initial condition, when the gate voltage (Vg) is raised, the drain current (Id) responds sharply at a certain area and the response characteristic called xe2x80x9cCut-Off characteristicxe2x80x9d can be assumed. However, after the cyclic operations of 10,000 times, such sharp cut-off characteristic is clearly deteriorated. Namely, after the cyclic operations of 10,000 times, the drain current (Id) only rises gradually and does not rise sharply from a constant value of the gate voltage (vg) even if a gate voltage (vg) rises.
Referring to FIG. 2
FIG. 2 is a graph (No. 2) indicating the read characteristic of the SONOS type non-volatile memory of the related art. As likely as shown in the FIG. 1, a gate voltage is plotted on the horizontal axis, while a drain current on the vertical axis and the characteristic (indicated with a solid line) in the condition (deterioration) before the start of use and the characteristic (indicated with a chain line) after the cyclic operations of 10,000 times are compared schematically on the same graph. Deterioration of the cut-off characteristic becomes a cause, as illustrated in FIG. 2, of completion of verification even if storage of charges is insufficient during the verify read operation. Namely, when the sharp cut-off characteristic similar to that before deterioration is obtained for a constant value of drain voltage (reference current), the adequate gate voltage not reaching the write level can be detected but after the cut-off characteristic is deteriorated, if the value of gate voltage does not reach the write level for the reference current value of the drain current, it is erroneously assumed that such gate voltage has reached the write level.
However, it has been known that deterioration of the cut-off characteristic can be recovered through the heat treatment.
Referring to FIG. 3
FIG. 3 is a graph (No. 3) indicating the read characteristic of the SONOS type non-volatile memory of the related art. Similar to FIG. 1 and FIG. 2, a gate voltage (Vg) is plotted on the horizontal axis, while a drain current (Id) on the vertical axis. Here, the characteristic before the heat treatment (solid line and white angular points in the figure) and the characteristic after the heat treatment (dotted line and black angular points in the figure) are indicated on the same graph for comparison. From FIG. 3, it can be understood that the cut-off characteristic may be improved with the heat treatment. Namely, even when the drain current (Id) shows only gradual change for change of gate voltage (Vg) through the cyclic operations of considerable number of times before the heat treatment and the cut-off characteristic is sufficiently deteriorated, the graph is curved at the constant value of the gate voltage (Vg) after the heat treatment, and thereby it will be understood that the good cut-off characteristic in which the drain current (Id) quickly responds is recovered.
The fact indicated with the experiment that the cut-off characteristic is improved with the heat treatment as explained above means that the threshold value after the verify write operation shifts in the negative direction due to the thermal stress and thereby the window margin of the erase condition and write condition becomes narrow. Namely, deterioration in the cut-off characteristic will result in the problem, namely, deterioration of retention.
As explained above, it has been proved that the related art has the problems that it is impossible to accurately verify whether the data has been written accurately or not and that the data retention characteristic is deteriorated. Therefore, the present invention has been proposed to solve the problems explained above, reserve the accurate data verify and good data retention as the characteristic and always provide the equal and good read characteristic even when the first gate oxide film and interface are deteriorated due to the device operations such as data write and erase operations.
The present invention is intended to solve the problems explained above, for example, with the following means.
(1) A non-volatile semiconductor memory device (EEPROM) including a memory cell array arranging a plurality of memory cells, enabling electrical reprogramming through the transfer of charges between a charge trap layer and a semiconductor substrate, in the form of matrix, each of such cells is formed by sequentially laminating, on the semiconductor substrate, a first gate oxide film, the charge trap layer consisting of an insulation material which traps charges more easily than a silicon oxide film, a gate insulation film consisting of a second gate oxide film and a gate electrode, wherein after data is written to the memory cell, electrons are partly removed from the charge trap layer.
(2) A non-volatile semiconductor memory device as described in item (1), comprising, under the condition of 0xe2x89xa6|Vws|xe2x89xa6|Vwe|, 0xe2x89xa6|Vbs|xe2x89xa6|Vbe|, tsxe2x89xa6te:
a means for writing data to the memory cells by applying voltages Vwp to the gate electrode and Vdp to the drain of the memory cells, a means for erasing data from the memory cells by applying for te seconds the erase voltages Vwe to the gate insulation film and Vbe to the source and drain of the memory cells, and a means for removing a part of the electrons by applying for ts seconds the voltage Vwe to the gate insulation film and the voltage Vbs to the source and drain after the data writing operation.
(3) A non-volatile semiconductor memory device as described in item (2), wherein a part of electrons is removed under the voltage condition of Vbs=Vdp.
(4) A non-volatile semiconductor memory device as described in items (1) to (3), wherein after data is written to the memory cell array on the occasion of executing the verify write operation, a part of the electrons is removed and verify operation is performed and such operations are repeated until the data is written sufficiently.
(5) A data holding method of a non-volatile semiconductor memory device for applying, for a short period of time, a voltage equal to the voltage to erase the data stored in the memory cell, in order to remove a part of the electrons, to the a non-volatile semiconductor memory device (EEPROM) including a memory cell array arranging a plurality of memory cells, enabling electrical reprogramming through the transfer of charges between a charge trap layer and a semiconductor substrate, in the form of matrix, each of such cells is formed by sequentially laminating, on the semiconductor substrate, a first gate oxide film, the charge trap layer consisting of an insulation material which traps charges more easily than a silicon oxide film, a gate insulation film consisting of a second gate oxide film and a gate electrode.
(6) A data holding method of the non-volatile semiconductor memory device as described in item (5), comprising, under the condition of 0xe2x89xa6|Vws|xe2x89xa6|Vwe|, 0xe2x89xa6|Vbs|xe2x89xa6|Vbe|, tsxe2x89xa6te:
a means for writing data to the memory cells by applying voltages Vwp to the gate electrode and Vdp to the drain of the memory cells, a means for erasing data from the memory cells by applying for te seconds the erase voltages Vwe to the gate insulation film and Vbe to the source and drain of the memory cells, and a means for removing a part of the electrons by applying for ts seconds the voltage Vwe to the gate insulation film and the voltage Vbs to the source and drain after the data writing operation.
(7) A data holding method of the non-volatile semiconductor memory device as described in item (6), wherein a part of electrons is removed under the voltage condition of Vbs=Vdp.
(8) A data holding method of the non-volatile semiconductor memory device as described in items (5) to (7), wherein after data is written to said memory cell array on the occasion of executing data verify operation, a part of the electrons is removed and verify operation is performed and such operations are repeated until the data is written sufficiently.
Next, operations of the present invention will be explained. The characteristics of the present invention may be summarized as follows. After the data write operation of a non-volatile semiconductor memory (EEPROM) using a charge storing insulation film in place of a gate insulation film in the related art, a potential corresponding to application to a memory cell in order to data erase is given, for example, to the memory cell for only a moment and thereby the read characteristic can be improved. Effect of such improvement in the read characteristic is peculiar to the non-volatile semiconductor memory (EEPROM) using the charge storing insulation film in place of the gate insulation film of the related art and the similar improvement in the read characteristic cannot be attained even when the operation to give the pulse corresponding to the data erase potential to the memory cell after data write operation is conducted for the EEPROM of the related art. Namely, the finding of improvement in the read characteristic of the present invention is sufficiently considered as the novel finding attained after investigations by the inventors of the present invention but the principle thereof is not yet sufficiently proved.
Referring Again to FIG. 1
As illustrated in FIG. 1, in the memory cell, like the SONOS type memory cell, where an insulation film that can trap electrons more easily than a silicon oxide film is provided on a gate oxide film and it is then used as the electron trap, it has been confirmed by experiment that deterioration at the interface gives a large influence on the read characteristic of the memory cell. However, it is also confirmed by experiment that the read characteristic can be improved by conducting, although identical to the data erase operation, the stress operation (called the xe2x80x9cpost write operationxe2x80x9d) composed of the gate voltage which is alleviated in comparison with the data erase operation or drain voltage or extremely shortened application pulse width after the data write operation.
Referring to FIG. 4
FIG. 4 illustrates a graph (No. 1) indicating the read characteristic of the SONOS type non-volatile memory of the present invention. In the FIG. 4, a gate voltage (Vg) is plotted on the horizontal axis and a drain current (Id) on the vertical axis. The initial condition, namely condition before start of use is indicted with a dotted line, the condition after data write with a fine solid line and the condition after the soft erase, i.e., after inputting the post write pulse, with a thick solid line. As illustrated in FIG. 4, it can be understood that the sharp cut-off characteristic in the condition before start of use (initial condition) is deteriorated by aging through the update of data and response of the drain current (Id) for increase of the gate voltage (Vg) is very much deteriorated but the read characteristic is improved because the post write pulse in the present invention is inputted after the data write operation.
As explained above, it has been proved by the experiment that when the post write pulse is inputted after application of the pulse for data write operation in order to realize the data write operation, the read characteristic is improved. It has not yet been clearly found that the reason. why the post write pulse is effective for reliable holding of the stored data. Instead, the significant effect of the post write pulse has been recognized as a result of the inventors"" several experiments.
By the way, the sufficient effect cannot be obtained if such post-write pulse is given for the longer time. If the post-write operation pulse is given for a longer period, electrons injected to the nitride film for the data writing are pulled out and the threshold voltage is shifted in the negative direction. Therefore, the pulse for post-write operation must be shorter than the pulse for erase operation. It has also been proved by the experiment and the reason will be explained with reference to FIG. 5.
Referring to FIG. 5
FIG. 5 is a graph indicating the threshold value characteristic of the SONOS type non-volatile memory of the present invention. In FIG. 5, the time for giving an erase potential to the memory cell after data write (pulse length: ts) is plotted on the horizontal axis, while a threshold value potential (V) and S coefficient (mV/dec) on the vertical axis to show the relationship between these values. Change of the threshold voltage (V) for pulse length ts (sec) is indicated by the graph connecting the write points. Meanwhile, change of S coefficient (mV/dec) for the pulse length ts (sec) is indicated by the graph connecting the black points. Voltage condition of the pulse given to the memory cell after data write (hereinafter referred to as xe2x80x9cpost-write pulsexe2x80x9d) is not always required to be identical to the voltage condition to be given to the memory cell at the time of data erase operation and the potential which pulls out the charges to the substrate from the charge storage film of the memory cell will provide sufficient effect of the present invention even if the voltage condition is different. However, when the voltage condition of post-write pulse is identical to the voltage condition at the time of data erase, only the time control for the pulse is basically required and therefore it is preferable because the effect that the circuit structure is simplified can be obtained as an accompanying effect. Therefore, when the voltage condition of post-write pulse is identical to that at the time of erase operation, it is explained as a first example. When ts less than 1xc3x9710xe2x88x926 sec=ts0 from FIG. 5, it can be understood that the threshold voltage does not return to the initial condition but the S coefficient is recovered. Accordingly, when the voltage condition of the post-write operation is set identical to that of the erase operation, ts less than ts0 is the preferable condition. ts0 is equal to {fraction (1/10000)}of the ordinary erase time te.
Here, the post-write pulse means for improving only the read characteristic without pulling out the electrons injected to the nitride film as positively as erasing the data can also be realized by alleviating the gate voltage or the drain voltage of the memory cell in comparison with the voltage in the erase operation, in addition to adjustment of the pulse width to the short period in the same manner as the voltage relationship during the data erase operation. Namely, when the word line voltage for the post-write pulse is defined as Vws, the bit line voltage as Vbs, the word line voltage Vwe in the erase operation and the bit line voltage as Vbe, only the read characteristic can be improved without pulling out the electrons injected to the nitride film as positively as erasing the data by setting stress condition of the post-write operation as satisfying the relationships such as |Vws| less than |Vwe|, Vbs| less than |Vbe|.
In more practical, when the post-write pulse is added after the data writing, the all bit lines of the selected memory cell block are set to Vbs and Vws is applied to all word lines. In this case, the p-type substrate (or p-type well and n-type substrate) formed on this memory cell block is grounded. Thereby, the excellent and constant read characteristic of the memory cell can be obtained.
As explained above, the present invention provides the effect that the write data holding characteristic of the electrically erasable/programmable non-volatile memory (EEPROM) can be improved substantially without change of manufacturing process of the memory cell array. Moreover, it is also possible to obtain similar effect even by giving a potential similar to the erase potential and shortening only the pulse length, together with the accompanying effect in the present invention that generation of pulse can be controlled at the outside of the EEPROM without requiring, in this case, a new provision of the voltage boosting circuit or the like for such object.
Moreover, in the present invention, it is no longer required to self-completely execute the control by conducting the timing control using external clock such as CPU clock or the like. Therefore, following additional effects can also be attained that the peripheral circuits in the EEPROM can be simplified and general purpose EEPROM can be used in direct.